(1) Field of the invention
The present invention relates to an information processing apparatus and an (electric) power consumption computation method for the information processing apparatus.
In particular, when a CPU (Central Processing Unit) command is effectively executed, such an information processing apparatus can estimate power consumption, which is one of system information items, for each work load (i.e., application).
(2) Description of Related Art
Recently, in accordance with increasing concern about global warming and growing consciousness for energy conservation, it is required to accurately compute (electric) power consumed by an ICT (Information and Communication Technology) device.
Conventionally, such power consumed by an ICT device has been computed by estimating it utilizing, for example, rated power of a power supply or by attaching a sensor to a connector of a power supply cord. However, for a logical management unit (e.g., a program or a process) graspable by the user, power management has not been accurately managed. More specifically, total power consumption has been distributed into individual management units while applying a certain assumption to logical management units.
Additionally, in recent information processing systems which employ developed virtualization, it is required to obtain power consumption of each individual virtual machine.
As a known technique of the relevant technical field, Patent Document 1 discloses high-speed estimation of power consumption of a large-scaled semiconductor integrated circuit when designing the semiconductor integrated circuit utilizing a processor core or a megacell core.
More specifically, a device is provided to simulate a process executed by a processor unit and compute power consumed by the processor unit by referring to power consumption information of the processor unit, that is obtained in advance. Another device is also provided to simulate a functional block and compute power consumption based on power consumption information for each individual state of part of input pins or output pins of the functional block at its operation level. Another device is further provided to compute power consumption based on power consumption information for each logic gate and the number of times of toggling in a signal output from the logic gate. Another device is also provided to sum the power consumption values of individual blocks and output the result thereof. The operations by the above devices are repeated until execution of program codes simulated by the relevant processor is completed, and thereby power consumed by the entire circuit is computed.
In addition, Patent Document 2 discloses a logic design apparatus for estimating power consumed by a device.
More specifically, a secondary power supply that supplies power, a circuit that measures power consumption, and a voltmeter/ammeter are provided to electrically rewritable logic devices mounted on an emulator, and an MPU (microprocessor unit) or ICE (in-circuit emulator) function is applied to the logic devices. A software application is performed on the emulator and the voltmeter/ammeter measures power consumption required for executing a predetermined command unit of the performed software application. A power consumption summation unit computes a maximum value, a minimum value, and an average of the measured power consumption. A display unit displays the measured power consumption on a screen of a memory window provided at a source code debugger of an in-circuit emulator. Based on a power consumption conversion table stored in a conversion table storage unit, the power consumption summation unit converts the measured power consumption to power consumed by a target device (final product) such as an LSI.
In addition, Patent Document 3 discloses a method used in a processor that includes an MMU (memory management unit) and a cache memory and converts each logical address to a physical address. In the method, power consumption of a semiconductor integrated circuit of the processor is estimated at a high speed at an architectural level.
More specifically, power consumption information on each MMU operation in the MMU is prepared in advance, and a write back mode and a write through mode are distinguished from each other in a cache unit. In addition, power consumption information on each cache operation (that includes writing of dirty data) is prepared, and power consumption information about each command of the UPU is also utilized. Accordingly, during or after the simulation, power consumed in the entire circuit as the target for the simulation is computed based on the power consumption information.